module led_alternate (
    input  wire clk_50m,
    output reg  led1,
    output reg  led2
);

    // 50 MHz × 25 ms = 1,250,000
    localparam COUNT_MAX = 5_000_000 - 1;

    reg [31:0] counter = 0;

    initial begin
        led1 = 1'b1;
        led2 = 1'b0;
    end

    always @(posedge clk_50m) begin
        if (counter >= COUNT_MAX) begin
            counter <= 0;

            led1 <= ~led1;
            led2 <= ~led2;
        end
        else begin
            counter <= counter + 1'b1;
        end
    end

endmodule